A ZK Hardware case study
Background
Aleo is an L1 blockchain with the goal of enabling expressive privacy preserving applications. Aleo pioneered the concept of KZG puzzles, in which, as part of Aleo consensus mechanism, provers are competing to solve a ZK coinbase puzzle. The most cost-efficient provers gain more rewards. This unique mechanism is the only instance, as of today, to generate a leveled playing field and enough demand for ZK proofs, to drive an apples-to-apples comparison between different acceleration techniques. We had the privilege of participating in Aleo testnet with our GPU provers. Today we introduce the next phase.
Meet the Bride
Aleo IP is aimed for ASIC platforms running Aleo testnet puzzles. This IP features a parameterized RTL design that achieves state-of-the-art performance and power efficiency. The design was synthesized using a tool compatible with the TSMC 7nm process running at 1.2 GHz.
The Aleo IP is composed of:
- A single miner manager that is responsible for the user interface and the management of the whole logic.
- A number of Aleo cores — the number of Aleo cores is a parameter determined by the user. A single Aleo core generates an Aleo proof from the initial seed to the final elliptic curve point.
ALEO IP high level spec table:
Competing hardware comparison:
Notes:
- The numbers provided for Aleo IP are for N Aleo cores. The area of the Miner Manager mostly depends on the SRAM memory that the user will use for this module.
- The GPU data is based on the recorded data from Aleo testnet3 (December 2022). Since then, there has been significant work on algorithm research, resulting in up to 2x better performance.
For access to our FPGA simulator, further details and business inquiries, feel free to send an email to hi@ingonyama.com
Departing thoughts: Why we chose IP Core and not tapeout
This is a simple risk vs. reward decision. We do not have guarantees that the same puzzle used in the testnet will also be deployed in mainnet. In fact, all signals indicate a change in puzzle before mainnet launch.
ZK is a moving target and it is our goal as a company to adjust the pace of hardware innovation accordingly. Delivering an IP Core allowed us to explore the ZK hardware design space in depth we never reached before and discover new partners eager to learn how operating a ZK data center is going to be like. In addition, it gives us, and the community, a good benchmark comparing ZK ASIC and GPU.
